SH7080_09 Datasheet, PDF (31/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Figure 8.13 Example of DTC Operation Timing: Normal or Repeat Transfer
in Short Address Mode (Activated by On-Chip Peripheral Module;
Iφ: Bφ: Pφ =1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module
to On-Chip RAM; Transfer Information is Written in 3 Cycles) ............................ 202
Figure 8.14 Example of DTC Operation Timing: Normal or Repeat Transfer with DTPR = 1
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles) .......................................................... 203
Figure 8.15 Example of DTC Operation Timing: Normal or Repeat Transfer
(Activated by IRQ; Iφ: Bφ: Pφ =1: 1/2: 1/2; Data Transferred from On-Chip
Peripheral Module to On-Chip RAM; Transfer Information is
Written in 3 Cycles) ................................................................................................ 203
Figure 8.16 Example of DTC Operation Timing: Conflict of Two Activation Requests in
Normal Transfer Mode (Activated by On-Chip Peripheral Module;
Iφ: Bφ: Pφ = 1: 1/2: 1/2; Data Transferred from On-Chip Peripheral Module
to On-Chip RAM; Transfer Information is Written in 3 Cycles) ........................... 208
Figure 8.17 Example of DTC Activation in Accordance with Priority ...................................... 209
Figure 8.18 Activation of DTC by Interrupt............................................................................... 210
Figure 8.19 Chain Transfer when Counter = 0 ........................................................................... 212
Section 9 Bus State Controller (BSC)
Figure 9.1 Block Diagram of BSC ........................................................................................... 219
Figure 9.2 Normal Space Basic Access Timing (Access Wait 0)............................................. 288
Figure 9.3 Continuous Access for Normal Space 1 Bus Width = 16 Bits, Longword
\
Access, WM Bit in CSnWCR = 0 (Access Wait = 0, Cycle Wait = 0) ................... 290
Figure 9.4 Continuous Access for Normal Space 2 Bus Width = 16 Bits, Longword
Access, WM Bit in CSnWCR = 1 (Access Wait = 0, Cycle Wait = 0) ................... 291
Figure 9.5 Example of 32-Bit Data-Width SRAM Connection................................................ 292
Figure 9.6 Example of 16-Bit Data-Width SRAM Connection................................................ 293
Figure 9.7 Example of 8-Bit Data-Width SRAM Connection.................................................. 293
Figure 9.8 Wait Timing for Normal Space Access (Software Wait Only) ............................... 294
Figure 9.9 Wait State Timing for Normal Space Access (Wait State Insertion Using
WAIT Signal).......................................................................................................... 295
Figure 9.10 CSn Assert Period Extension .................................................................................. 296
Figure 9.11 Access Timing for MPX Space (Address Cycle No Wait, Data Cycle No Wait) ... 298
Figure 9.12 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait) ...... 299
Figure 9.13 Access Timing for MPX Space
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) .................... 300
Figure 9.14 Example of 32-Bit Data Width SDRAM Connection
(RASU and CASU are not Used) ............................................................................ 302
Rev. 4.00 Dec. 15, 2009 Page xxix of lviii
REJ09B0181-0400