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| SH7080_09 Datasheet, PDF (385/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family | |||
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CK
A25 to A0
A12/A11*1
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*2
Section 9 Bus State Controller (BSC)
Td1
Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.22 Burst Read Timing (No Auto-Precharge)
Rev. 4.00 Dec. 15, 2009 Page 325 of 1558
REJ09B0181-0400
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