SH7080_09 Datasheet, PDF (93/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
Addressing
Mode
Register
indirect with
displacement
Instruction
Format Effective Address Calculation Method
@(disp:4,
Rn)
Effective address is register Rn contents with
4-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
Rn
disp
(zero-extended)
+
Rn
+ disp × 1/2/4
×
Calculation
Formula
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn +
disp × 4
1/2/4
Index
@(R0, Rn) Effective address is sum of register Rn and R0 Rn + R0
register indirect
contents.
Rn
+
Rn + R0
R0
GBR indirect
with
displacement
@(disp:8,
GBR)
Effective address is register GBR contents with Byte: GBR + disp
8-bit displacement disp added. After disp is
zero-extended, it is multiplied by 1 (byte), 2
(word), or 4 (longword), according to the
operand size.
GBR
Word: GBR + disp ×
2
Longword: GBR +
disp × 4
disp
(zero-extended)
+
GBR
+ disp × 1/2/4
×
Index GBR
indirect
@(R0,
GBR)
1/2/4
Effective address is sum of register GBR and
R0 contents.
GBR
GBR + R0
+
GBR + R0
R0
Rev. 4.00 Dec. 15, 2009 Page 33 of 1558
REJ09B0181-0400