SH7080_09 Datasheet, PDF (1339/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
Interrupt acceptance
n
Fetch
n+1
Decoding
(a)
n+2
Execution
(b)
n+3
Execution
n+4
Execution
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Figure 23.21 Timing of Contention between SCO Download Request and Interrupt Request
2. Generation of interrupt requests during downloading
Ensure that interrupts are not generated during downloading that is initiated by the SCO
bit.
Rev. 4.00 Dec. 15, 2009 Page 1279 of 1558
REJ09B0181-0400