SH7080_09 Datasheet, PDF (338/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.4.7 Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is set to 1, a memory refresh request is issued by this matching
signal. This request is maintained until the refresh operation is performed. If the request is not
processed when the next matching occurs, the previous request is ignored.
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal.
The request is output continuously until the CMF bit in RTCSR is cleared. Clearing the CMF bit
only affects the interrupt request and does not clear the refresh request. Therefore, a combination
of refresh request and interval timer interrupt can be specified so that the number of refresh
requests are counted by using timer interrupts while refresh is performed periodically. When
writing to RTCOR, write data with setting the upper 16 bits to H'A55A to cancel write protection.
Bit: 31
-
Initial value: 0
R/W: R/W
30
-
0
R/W
29
-
0
R/W
28
-
0
R/W
27
-
0
R/W
26
-
0
R/W
25
-
0
R/W
24
-
0
R/W
23
-
0
R/W
22
-
0
R/W
21
-
0
R/W
20
-
0
R/W
19
-
0
R/W
18
-
0
R/W
17
-
0
R/W
16
-
0
R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to ⎯
16
All 0
R/W Write Protect Cancellation
When writing to RTCOR, write H'A55A to these bits to
cancel write protection. These bits are always read as 0.
15 to 8 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0
All 0
R/W 8-bit counter
Rev. 4.00 Dec. 15, 2009 Page 278 of 1558
REJ09B0181-0400