SH7080_09 Datasheet, PDF (1493/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

CK
A25 to A0
CSn
RDWR
RD
D31 to D0
WRxx
BS
DACKn*
TENDn*
WAIT
Section 28 Electrical Characteristics
T1
Tw
Twx
T2B
Twb
T2B
t_AD1
t_AD2
t_AD2
t_AD1
t_CSD t_AS
t_CSD
t_RWD
t_RSD
t_RWD
t_RDS3
t_RDH3
t_RSD
t_RDS3
t_RDH3
t_BSD
t_BSD
t_DACD
t_WTH
t_WTH
t_WTS
t_WTS
t_DACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 28.23 Burst ROM Read Cycle
(One Software Wait Cycle, One External Wait Cycle, One Burst Wait Cycle, Two Bursts)
Rev. 4.00 Dec. 15, 2009 Page 1433 of 1558
REJ09B0181-0400