SH7080_09 Datasheet, PDF(393/1622 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

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SH7080_09 Datasheet, PDF (393/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

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Section 9 Bus State Controller (BSC)

After self-refreshing has been specified, the SDRAM stays in the self-refresh state even after

this LSI enters the standby state. The self-refresh state continues after recovery from the

standby state by interrupt. However, the CKE and other pins must be driven in the standby

state by setting the HIZCNT bit in the CMNCR register to 1.

The self-refresh state is not cleared by a manual reset.

In case of a power-on reset, the bus state controllerâs registers are initialized, and therefore the

self-refresh state is cleared.

CK

CKE

A25 to A0

A12/A11*1

CSn

RASL, RASU

CASL, CASU

RDWR

DQMxx

D31 to D0

BS

DACKn*2

Tp

Tpw

Trr

Trc

Hi-Z

Trc

Trc

Trc

Trc

Notes: 1. Address pin to be connected to pin A10 of SDRAM.

2. The waveform for DACKn is when active low is specified.

Figure 9.29 Self-Refresh Timing

Rev. 4.00 Dec. 15, 2009 Page 333 of 1558

REJ09B0181-0400

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