SH7080_09 Datasheet, PDF (740/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 13 Port Output Enable (POE)
Figure 13.1 shows a block diagram of the POE.
TIOC3B
TIOC3D
TIOC4A
TIOC4C
TIOC4B
TIOC4D
TIOC3BS
TIOC3DS
TIOC4AS
TIOC4CS
TIOC4BS
TIOC4DS
POE3
POE2
POE1
POE0
Output level comparison circuit
Output level comparison circuit
Output level comparison circuit
Output level comparison circuit
Output level comparison circuit
Output level comparison circuit
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
POECR1,
POECR2
High-impedance
request signal for MTU2
high-current pins
High-impedance
request signal for MTU2
channel 0 pins
High-impedance
request signal
for MTU2S
high-current pins
Interrupt
request signal
POE7
POE6
POE5
POE4
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
POE8
Input level detection circuit
Falling edge
detection circuit
Low level
sampling circuit
[Legend]
ICSR1: Input level control/status register 1
ICSR2: Input level control/status register 2
ICSR3: Input level control/status register 3
OCSR1: Output level control/status register 1
OCSR2: Output level control/status register 2
Pφ/8
Pφ/16
Pφ/128
Frequency
divider
SPOER
Pφ
SPOER: Software port output enable register
POECR1: Port output enable control register 1
POECR2: Port output enable control register 2
Figure 13.1 Block Diagram of POE
Rev. 4.00 Dec. 15, 2009 Page 680 of 1558
REJ09B0181-0400