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| SH7080_09 Datasheet, PDF (1488/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family | |||
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Section 28 Electrical Characteristics
CK
A25 to A0
Ta1
Ta2
Ta3
T1
Tw
Tw
T2
tAD1
tAD1
tCSD
tCSD
CSn
tRWD
RDWR
tRWD
AH
tAHD
tAHD
tAHD
tAHD
RD
D15 to D0
WRxx
D15 to D0
BS
tRSD
tBSD
tMAD
tMAD
tBSD
Address
tMAH
tWSD1
tWDD1
tMAH
Address
Data
tRSD
tRDH1
tRDS1
Data
tWSD1
tWRH
tWDH1
WAIT
DACKn*
TENDn*
tDACD
tWTH
tWTS
tWTH
tWTS
tDACD
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 28.18 MPX-I/O Interface Bus Cycle
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1428 of 1558
REJ09B0181-0400
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