SH7080_09 Datasheet, PDF (400/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
T1
T2
CK
A29 to A0
CSn
WRxx
RDWR
Read
RD
D31 to D0
Write
RDWR
RD
High
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.32 Basic Access Timing for SRAM with Byte Selection (BAS = 0)
Rev. 4.00 Dec. 15, 2009 Page 340 of 1558
REJ09B0181-0400