SH7080_09 Datasheet, PDF (797/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
Initial
Bit
Bit Name value R/W Description
4
FER
0
R/(W)* Framing Error
Indicates that a framing error occurred during data
reception in asynchronous mode, causing abnormal
termination.
0: Indicates that reception is in progress or was
completed successfully*¹
[Clearing conditions]
• By a power-on reset or in standby mode
• When 0 is written to FER after reading FER = 1
1: Indicates that a framing error occurred during
reception
[Setting condition]
• When the SCI founds that the stop bit at the end
of the received data is 0 after completing
reception*²
Notes: 1. The FER flag is not affected and retains
its previous value when the RE bit in
SCSCR is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is
checked for a value to 1; the second stop
bit is not checked. If a framing error
occurs, the receive data is transferred to
SCRDR but the RDRF flag is not set.
Subsequent serial reception cannot be
continued while the FER flag is set to 1.
Rev. 4.00 Dec. 15, 2009 Page 737 of 1558
REJ09B0181-0400