SH7080_09 Datasheet, PDF (950/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.4.6 SCS Pin Control and Conflict Error
When bits CSS1 and CSS0 in SSCRH are set to B'10 and the SSUMS bit in SSCRL is cleared to
0, the SCS pin becomes an input pin (Hi-Z) before the serial transfer is started and after the serial
transfer is complete. Because of this, the SSU performs conflict error detection during these
periods. If a low level signal is input to the SCS pin during these periods, it is detected as a
conflict error. At this time, the CE bit in SSSR is set to 1 and the MSS bit is cleared to 0.
Note: While the CE bit is set to 1, transmission or reception is not resumed. Clear the CE bit to 0
before resuming the transmission or reception.
External input to SCS
Internally-clocked SCS
MSS
Internal signal for
transfer enable
CE
Data written
to SSTDR
SCS output
(Hi-Z)
Conflict error
detection period
Worst time for
internal clocking of SCS
Figure 17.10 Conflict Error Detection Timing (Before Transfer)
Rev. 4.00 Dec. 15, 2009 Page 890 of 1558
REJ09B0181-0400