SH7080_09 Datasheet, PDF (101/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
Type
Branch
instructions
System
control
instructions
Total:
Kinds of
Instruction
9
Op Code
BF
BT
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
11
CLRT
CLRMAC
LDC
LDS
NOP
RTE
SETT
SLEEP
STC
STS
TRAPA
62
Function
Number of
Instructions
Conditional branch, delayed conditional 11
branch (T = 0)
Conditional branch, delayed conditional
branch (T = 1)
Unconditional branch
Unconditional branch
Branch to subroutine procedure
Branch to subroutine procedure
Unconditional branch
Branch to subroutine procedure
Return from subroutine procedure
T bit clear
31
MAC register clear
Load into control register
Load into system register
No operation
Return from exception handling
T bit setting
Transition to power-down mode
Store from control register
Store from system register
Trap exception handling
142
Rev. 4.00 Dec. 15, 2009 Page 41 of 1558
REJ09B0181-0400