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SH7080_09 Datasheet, PDF (110/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family | |||
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Section 2 CPU
2.5.7 System Control Instructions
Table 2.16 System Control Instructions
Instruction
CLRT
CLRMAC
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
NOP
RTE
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC.L SR,@âRn
STC.L GBR,@âRn
STC.L VBR,@âRn
Operation
Code
0âT
0000000000001000
0 â MACH, MACL
0000000000101000
Rm â SR
0100mmmm00001110
Rm â GBR
0100mmmm00011110
Rm â VBR
0100mmmm00101110
(Rm) â SR, Rm + 4 â Rm 0100mmmm00000111
(Rm) â GBR, Rm + 4 â
Rm
0100mmmm00010111
(Rm) â VBR, Rm + 4 â
Rm
0100mmmm00100111
Rm â MACH
0100mmmm00001010
Rm â MACL
0100mmmm00011010
Rm â PR
0100mmmm00101010
(Rm) â MACH, Rm + 4 â 0100mmmm00000110
Rm
(Rm) â MACL, Rm + 4 â 0100mmmm00010110
Rm
(Rm) â PR, Rm + 4 â Rm 0100mmmm00100110
No operation
0000000000001001
Delayed branch,
Stack area â PC/SR
0000000000101011
1âT
0000000000011000
Sleep
0000000000011011
SR â Rn
0000nnnn00000010
GBR â Rn
0000nnnn00010010
VBR â Rn
0000nnnn00100010
Rnâ4 â Rn, SR â (Rn) 0100nnnn00000011
Rnâ4 â Rn, GBR â (Rn) 0100nnnn00010011
Rnâ4 â Rn, VBR â (Rn) 0100nnnn00100011
Execution
Cycles T Bit
1
0
1
â¯
6
LSB
4
â¯
4
â¯
8
LSB
4
â¯
4
â¯
1
â¯
1
â¯
1
â¯
1
â¯
1
â¯
1
â¯
1
â¯
5
â¯
1
1
4*
â¯
1
â¯
1
â¯
1
â¯
1
â¯
1
â¯
1
â¯
Rev. 4.00 Dec. 15, 2009 Page 50 of 1558
REJ09B0181-0400
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