SH7080_09 Datasheet, PDF (285/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Address
Area
Memory Type
Capacity
Bus
Width
H'0E000000 to Reserved
H'1BFFFFFF
H'1C000000 to CS7 space
H'1DFFFFFF
Normal space
SRAM with byte selection
32 Mbytes 8 or 16
bits*
H'1E000000 to Reserved
H'FFF7FFFF
H'FFF80000 to SDRAM mode setting
H'FFF9FFFF space
H'FFFA0000 to Reserved
H'FFFF3FFF
H'FFFF4000 to On-chip RAM
H'FFFFBFFF
32 Kbytes 32 bits
H'FFFFC000 to On-chip peripheral
H'FFFFFFFF modules
16 Kbytes
8 or 16
bits
Notes: Do not access the reserved area. If the reserved area is accessed, the correct operation
cannot be guaranteed. In single-chip mode, only the on-chip ROM, on-chip RAM, and on-
chip peripheral modules can be accessed; the other areas cannot be accessed.
* The bus width is selected by the register setting.
Table 9.5 Address Map: SH7083 (512-Kbyte Flash Memory Version) in On-Chip ROM-
Disabled Mode
Address
H'00000000 to
H'01FFFFFF
Area
CS0 space
H'02000000 to
H'0BFFFFFF
H'0C000000 to
H'0DFFFFFF
Reserved
CS3 space
H'0E000000 to Reserved
H'1BFFFFFF
Memory Type
Normal space
SRAM with byte selection
Burst ROM (asynchronous)
Burst ROM (synchronous)
Capacity
32 Mbytes
Bus
Width
8 or 16
bits*¹
Normal space
SRAM with byte selection
SDRAM
32 Mbytes
8 or 16
bits*²
Rev. 4.00 Dec. 15, 2009 Page 225 of 1558
REJ09B0181-0400