SH7080_09 Datasheet, PDF (378/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
latched can be specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0
bits in CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR. The number of cycles from Tc1 to
Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency for the synchronous
DRAM is normally defined as up to three cycles. However, the CAS latency in this LSI can be
specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a latch circuit between
this LSI and the SDRAM.
A Tde cycle is an idle cycle required to transfer the read data into this LSI and occurs once for
every burst read or every single read.
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Td1 Td2
Td3
Td4
Tr
Tc1
Tc2
Tc3
Tc4
Tde
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.17 Burst Read Basic Timing (Auto-Precharge)
Rev. 4.00 Dec. 15, 2009 Page 318 of 1558
REJ09B0181-0400