SH7080_09 Datasheet, PDF (1599/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Main Revisions for this Edition
Item
Page
1.1 Features of SH7083, 6
SH7084, SH7085, and
SH7086
Table 1.1 Features
Revision (See Manual for Details)
Table amended
Items
I²C bus interface 2
(I²C2)
(SH7084, SH7085,
and SH7086 only)
Power supply voltage
Specification
• Conforming to Philips I²C bus interface
• Master mode and slave mode supported
• Continuous transfer
• I²C bus format or clock synchronous serial format selectable
• One channel
• Vcc: 3.0 to 3.6 V or 4.0 to 5.5 V
• AVcc: 4.0 to 5.5 V
1.2 Block Diagram
7
Figure 1.1 Block
Diagram
Figure note added
Peripheral bus (Pφ)
8.2.1 DTC Mode
174
Register A (MRA)
8.7.2 Chain Transfer 212
when Counter = 0
I/O
port
(PFC)
SCI SCIF CMT H-UDI INTC Power- WDT CPG MTU2 MTU2S POE SSU I²C2 ADC
*¹
down
*³
mode
control
[Legend]
ROM:
RAM:
UBC:
AUD:
H-UDI:
INTC:
CPG:
WDT:
CPU:
BSC:
DMAC:
On-chip ROM
On-chip RAM
User break controller
Advanced user debugger
User debugging interface
Interrupt controller
Clock pulse generator
Watchdog timer
Central processing unit
Bus state controller
Direct memory access controller
DTC: Data transfer controller
PFC: Pin function controller
MTU2: Multi-function timer pulse unit 2
MTU2S: Multi-function timer pulse unit 2 (subset)
POE: Port output enable
SCI: Serial communication interface
SCIF: Serial communication interface with FIFO
SSU: Synchronous serial communication unit
I²C2: I²C bus interface 2
CMT: Compare match timer
ADC: A/D converter
Notes: 1. Only in F-ZTAT version
2. Only in F-ZTAT version supporting full functions of E10A
3. SH7084, SH7085, and SH7086 only
Table amended
Initial
Bit Bit Name Value
R/W
7, 6 MD[1:0] Undefined ⎯
Description
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal transfer mode
01: Repeat transfer mode
10: Block transfer mode
11: Setting prohibited
Description amended
4. ... Set the upper eight bits of the transfer destination
address for the first data transfer to H'21. ...
5. ... Set the upper eight bits of the transfer destination
address for the first data transfer to H'20.
Rev. 4.00 Dec. 15, 2009 Page 1539 of 1558
REJ09B0181-0400