SH7080_09 Datasheet, PDF (794/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
15.3.7 Serial Status Register (SCSSR)
SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state.
The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF,
ORER, PER, and FER. These flags can be cleared to 0 only after 1 is read from the flags. The
TEND flag is a read-only bit and cannot be modified.
Bit: 7
6
5
4
3
2
1
0
TDRE RDRF ORER FER PER TEND MPB MPBT
Initial value: 1
0
0
0
0
1
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R
0
0
R R/W
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name value R/W Description
7
TDRE
1
R/(W)* Transmit Data Register Empty
Indicates whether data has been transferred from the
transmit data register (SCTDR) to the transmit shift
register (SCTSR) and SCTDR has become ready to
be written with next serial transmit data.
0: Indicates that SCTDR holds valid transmit data
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When data is written to SCTDR by a TXI interrupt
through the DMAC
• When the DTC is activated by a TXI interrupt and
transmit data is transferred to SCTDR while the
DISEL bit of MRB in the DTC is 0
1: Indicates that SCTDR does not hold valid transmit
data
[Setting conditions]
• By a power-on reset or in standby mode
• When the TE bit in SCSCR is 0
• When data is transferred from SCTDR to SCTSR
and data can be written to SCTDR
Rev. 4.00 Dec. 15, 2009 Page 734 of 1558
REJ09B0181-0400