SH7080_09 Datasheet, PDF (920/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
Figure 17.1 shows a block diagram of the SSU.
Module data bus
Internal data bus
SSTDR 0
SSTDR 1
SSTDR 2
SSTDR 3
SSRDR 0
SSRDR 1
SSRDR 2
SSRDR 3
SSCRH
SSCRL
SSCR2
SSMR
SSER
SSSR
Control circuit
SSOEI
SSCEI
SSRXI
SSTXI
SSTEI
SSTRSR
Selector
Clock
Clock
selector
Pφ
Pφ/4
Pφ/8
Pφ/16
Pφ/32
Pφ/64
Pφ/128
Pφ/256
SSI
SSO
SCS
[Legend]
SSCRH:
SS control register H
SSCRL:
SS control register L
SSCR2:
SS control register 2
SSMR:
SS mode register
SSER:
SS enable register
SSSR:
SS status register
SSTDR0 to SSTDR3: SS transmit data registers 0 to 3
SSRDR0 to SSRDR3: SS receive data registers 0 to 3
SSTRSR:
SS shift register
SSCK (External clock)
Figure 17.1 Block Diagram of SSU
Rev. 4.00 Dec. 15, 2009 Page 860 of 1558
REJ09B0181-0400