SH7080_09 Datasheet, PDF (153/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 5 Exception Handling
5.3 Address Errors
5.3.1 Address Error Sources
Address errors occur when instructions are fetched or data is read from or written to, as shown in
table 5.6.
Table 5.6 Bus Cycles and Address Errors
Bus Cycle
Type
Bus Master Bus Cycle Description
Instruction CPU
fetch
Instruction fetched from even address
Instruction fetched from odd address
Instruction fetched from a space other than
on-chip peripheral module space
Instruction fetched from on-chip peripheral
module space
Instruction fetched from external memory
space in single chip mode
Data
CPU, DMAC, Word data accessed from even address
read/write or DTC
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Byte or word data accessed in on-chip
peripheral module space
Longword data accessed in 16-bit on-chip
peripheral module space
Longword data accessed in 8-bit on-chip
peripheral module space
External memory space accessed when in
single chip mode
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
None (normal)
None (normal)
Address error occurs
Rev. 4.00 Dec. 15, 2009 Page 93 of 1558
REJ09B0181-0400