SH7080_09 Datasheet, PDF (1600/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
9.4.3 CSn Space Wait
Control Register
(CSnWCR) (n = 0 to 8)
(6) Burst MPX-I/O
Page
268
10.3.5 DMA Operation 396
Register (DMAOR)
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name
Value R/W Description
19
MPXMD
0
R/W Burst MPX-I/O Interface Mode Specification
This bit specifies the number of bursts per access. This
setting has effect only when the DMAC is set to the 16-
byte transfer unit size. When other transfer unit size is
selected, the setting of the MPXMD bit is ignored and
there is always one burst per access.
0: Four bursts per access
Four consecutive data cycles occur after the
address cycle.
1: Two bursts per access
Two consecutive data cycles occur after the
address cycle.
The correspondence between the data (D31 to D29)
output in the address cycle and the transfer size is
shown below.
D31 D30 D29 Transfer Size
0
0
0
Byte (one byte)
0
0
1
W ord (two bytes)
0
1
0
Longword (four bytes)
0
1
1
Quadw ord (eight bytes)
(only when MPXMD = 1)
1
0
0
16 bytes (only when
MPXMD = 0)
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Table amended
Initial
Bit
Bit Name Value R/W Description
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can be
done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI interrupt
was input.
0: No NMI interrupt
[Clearing condition]
• Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
Note: If the NMIF bit is read at the same point in time that it
is set to 1, in some cases the read value will be 0 but
the internal state will be as if it was read as 1.
Therefore, subsequently writing 0 to NMIF will clear it
to 0 in the same way as writing 0 to the flag after
reading it as 1. To prevent the NMIF bit from being
cleared to 0 inadvertently, always write 1 to the NMIF
bit except in cases when explicitly clearing it. To
explicitly clear the NMIF bit, write 0 to it after reading
it as 1. Note that if the NMIF bit is not used, there is
no problem with always writing 0 to it (and writing 0 to
it after reading it as 1 explicitly to clear it).
Rev. 4.00 Dec. 15, 2009 Page 1540 of 1558
REJ09B0181-0400