SH7080_09 Datasheet, PDF (870/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive
bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
The SCBRR setting is calculated as follows:
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Asynchronous mode:
N=
Pφ
× 10⁶ - 1
64 × 2^2n-1 × B
• Clock synchronous mode:
N=
8×
Pφ
2^2n-1 × B
×
10⁶
-1
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting value should satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of
n, see table 16.3.)
Rev. 4.00 Dec. 15, 2009 Page 810 of 1558
REJ09B0181-0400