SH7080_09 Datasheet, PDF (988/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
TRS
ICDRT
ICDRS
ICDRR
User
processing
Slave transmit mode
9
1
2
3
4
5
6
7
8
9
A
A
Slave receive
mode
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data n
[3] Clear TEND
[4] Read ICDRR (dummy read) [5] Clear TDRE
after clearing TRS
Figure 18.10 Slave Transmit Mode Operation Timing (2)
Rev. 4.00 Dec. 15, 2009 Page 928 of 1558
REJ09B0181-0400