SH7080_09 Datasheet, PDF (1503/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Td1
Td2
Td3
Td4
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
t_AD1
Column
address
t_AD1
t_AD1
READ command
CSn
RDWR
RASx
CASx
DQMxx
t_CSD
t_RWD
t_RASD
t_CASD
t_DQMD
D31 to D0
BS
CKE
TDEANCDKnn^**22
t_BSD
t_DACD
t_CSD
t_RWD
t_CASD
t_DQMD
t_RDS2
t_RDH2
t_BSD
t_RDS2 t_RDH2
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.33 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1443 of 1558
REJ09B0181-0400