SH7080_09 Datasheet, PDF (54/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Table 11.40 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0........................ 509
Table 11.41 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0........................ 509
Table 11.42 Setting of Bits BTE1 and BTE0 .............................................................................. 512
Table 11.43 Register Combinations in Buffer Operation............................................................ 525
Table 11.44 Cascaded Combinations .......................................................................................... 529
Table 11.45 TICCR Setting and Input Capture Input Pins.......................................................... 530
Table 11.46 PWM Output Registers and Output Pins................................................................. 535
Table 11.47 Phase Counting Mode Clock Input Pins.................................................................. 539
Table 11.48 Up/Down-Count Conditions in Phase Counting Mode 1 ........................................ 540
Table 11.49 Up/Down-Count Conditions in Phase Counting Mode 2 ........................................ 541
Table 11.50 Up/Down-Count Conditions in Phase Counting Mode 3 ........................................ 542
Table 11.51 Up/Down-Count Conditions in Phase Counting Mode 4 ........................................ 543
Table 11.52 Output Pins for Reset-Synchronized PWM Mode .................................................. 546
Table 11.53 Register Settings for Reset-Synchronized PWM Mode .......................................... 546
Table 11.54 Output Pins for Complementary PWM Mode......................................................... 549
Table 11.55 Register Settings for Complementary PWM Mode................................................. 550
Table 11.56 Registers and Counters Requiring Initialization...................................................... 556
Table 11.57 MTU2 Interrupts ..................................................................................................... 607
Table 11.58 Interrupt Sources and A/D Converter Start Request Signals................................... 610
Table 11.59 Mode Transition Combinations............................................................................... 640
Section 12 Multi-Function Timer Pulse Unit 2S (MTU2S)
Table 12.1 MTU2S Functions................................................................................................... 672
Table 12.2 Pin Configuration .................................................................................................... 675
Table 12.3 Register Configuration ............................................................................................ 676
Section 13 Port Output Enable (POE)
Table 13.1 Pin Configuration .................................................................................................... 681
Table 13.2 Pin Combinations .................................................................................................... 682
Table 13.3 Register Configuration ............................................................................................ 683
Table 13.4 Target Pins and Conditions for High-Impedance Control....................................... 705
Table 13.5 Interrupt Sources and Conditions ............................................................................ 710
Section 14 Watchdog Timer (WDT)
Table 14.1 WDT Pin Configuration .......................................................................................... 715
Table 14.2 Register Configuration ............................................................................................ 716
Section 15 Serial Communication Interface (SCI)
Table 15.1 Pin Configuration .................................................................................................... 725
Table 15.2 Register Configuration ............................................................................................ 726
Rev. 4.00 Dec. 15, 2009 Page lii of lviii
REJ09B0181-0400