SH7080_09 Datasheet, PDF (1284/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
(2) Download of On-Chip Program
The on-chip program is automatically downloaded by clearing VBR of the CPU to
H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS)
and the flash key code register (FKEY), which are programming/erasing interface registers.
The user MAT is replaced to the embedded program storage area when downloading. Since the
flash memory cannot be read when programming/erasing, the procedure program, which is
working from download to completion of programming/erasing, must be executed in a space
other than the flash memory to be programmed/erased (for example, on-chip RAM).
Since the result of download is returned to the programming/erasing interface parameters,
whether the normal download is executed or not can be confirmed.
Note that VBR can be changed after download is completed.
(3) Initialization of Programming/Erasing
The operating frequency and user branch are set before execution of programming/erasing.
The user branch destination must be in an area other than the user MAT area which is in the
middle of programming and the area where the on-chip program is downloaded. These settings
are performed by using the programming/erasing interface parameters.
(4) Programming/Erasing Execution
To program or erase, the FWE pin must be brought high and user program mode must be
entered.
The program data/programming destination address is specified in 128-byte units when
programming.
The block to be erased is specified in erase-block units when erasing.
These specifications are set by using the programming/erasing interface parameters and the on-
chip program is initiated. The on-chip program is executed by using the JSR or BSR
instruction to perform the subroutine call of the specified address in the on-chip RAM. The
execution result is returned to the programming/erasing interface parameters.
The area to be programmed must be erased in advance when programming flash memory.
There are limitations and notes on the interrupt processing during programming/erasing. For
details, see section 23.8.2, Interrupts during Programming/Erasing.
(5) When Programming/Erasing is Executed Consecutively
When the processing is not ended by the 128-byte programming or one-block erasure, the
program address/data and erase-block number must be updated and consecutive
programming/erasing is required.
Since the downloaded on-chip program is left in the on-chip RAM after the processing,
download and initialization are not required when the same processing is executed
consecutively.
Rev. 4.00 Dec. 15, 2009 Page 1224 of 1558
REJ09B0181-0400