SH7080_09 Datasheet, PDF (470/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.9 shows an example of DMA transfer timing in single address mode.
CK
A29 to A0
CSn
WRxx
D31 to D0
DACKn
Address output to external memory space
Select signal to external memory space
Write strobe signal to external memory space
Data output from external device with DACK
DACK signal (active-low) to external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
CK
A29 to A0
CSn
RD
Address output to external memory space
Select signal to external memory space
Read strobe signal to external memory space
D31 to D0
DACKn
Data output from external memory space
DACK signal (active-low) to external device with DACK
(b) External memory space (ordinary memory) → external device with DACK
Figure 10.9 Example of DMA Transfer Timing in Single Address Mode
Bus Modes: There are two bus modes: cycle steal mode and burst mode. Select the mode in the
TB bits in the channel control register (CHCR).
• Cycle-Steal Mode
⎯ Normal mode
In cycle-steal normal mode, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to the
other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the
transfer request source, transfer source, and transfer destination.
Figure 10.10 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
⎯ Dual address mode
⎯ DREQ low level detection
Rev. 4.00 Dec. 15, 2009 Page 410 of 1558
REJ09B0181-0400