SH7080_09 Datasheet, PDF (770/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 13 Port Output Enable (POE)
13.5 Interrupts
The POE issues a request to generate an interrupt when the specified condition is satisfied during
input level detection or output level comparison. Table 13.5 shows the interrupt sources and their
conditions.
Table 13.5 Interrupt Sources and Conditions
Name
OEI1
OEI3
OEI2
Interrupt Source
Output enable interrupt 1
Output enable interrupt 3
Output enable interrupt 2
Interrupt Flag
POE3F, POE2F, POE1F,
POE0F, and OSF1
POE8F
POE4F, POE5F, POE6F,
POE7F, and OSF2
Condition
PIE1 • (POE3F + POE2F +
POE1F + POE0F) + OIE1 •
OSF1
PIE3 • POE8F
PIE2 • (POE4F + POE5F +
POE6F + POE7F) + OIE2 •
OSF2
Rev. 4.00 Dec. 15, 2009 Page 710 of 1558
REJ09B0181-0400