SH7080_09 Datasheet, PDF (349/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in a 32-bit device or 16 bits are always read in a 16-bit device. When writing, only the WRxx
signal for the byte to be written is asserted.
It is necessary to control of outputing the data that has been read using RD when a buffer is
established in the data bus. The RDWR signal is in a read state (high output) when no access has
been carried out. Therefore, care must be taken when controlling the external data buffer using
RDWR, to avoid collision.
Figures 9.3 and 9.4 show the basic timings of continuous accesses to normal space. If the WM bit
in CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.3). If
the WM bit in CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.4).
Rev. 4.00 Dec. 15, 2009 Page 289 of 1558
REJ09B0181-0400