SH7080_09 Datasheet, PDF (1507/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
CK
A25 to A0
A12/A11^*1
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
Row address
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Column address
WRIT command
t_AD1
t_AD1
CSn
RDWR
RASx
CASx
DQMxx
D31 to D0
BS
CKE
TDEANCDKnn^**22
t_CSD
t_RWD
t_RWD
t_RWD
t_RASD
t_RASD
t_RASD
t_RASD
t_CASD
t_DQMD
t_WDD2
t_WDH2
t_BSD
t_DACD
(High)
t_CSD
t_RWD
t_CASD
t_DQMD
t_WDD2
t_WDH2
t_BSD
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 28.37 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)
Rev. 4.00 Dec. 15, 2009 Page 1447 of 1558
REJ09B0181-0400