SH7080_09 Datasheet, PDF (451/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Bit
Bit Name
11 to 8 RS[3:0]
Initial
Value
0000
R/W
R/W
Descriptions
Resource Select 3 to 0
Specify which transfer requests will be sent to the DMAC.
The changing of transfer request source should be done
in the state that the DMA enable bit (DE) is set to 0.
0 0 0 0 External request, dual address mode
0 0 0 1 Setting prohibited
0 0 1 0 External request, single address mode
External address space → External device with
DACK
0 0 1 1 External request, single address mode
External device with DACK → External address
space
0 1 0 0 Auto request
0 1 0 1 Setting prohibited
0 1 1 0 MTU2 (TGIA_0)
0 1 1 1 MTU2 (TGIA_1)
1 0 0 0 MTU2 (TGIA_2)
1 0 0 1 MTU2 (TGIA_3)
1 0 1 0 MTU2 (TGIA_4)
1 0 1 1 A/D_1 (ADI_1)
1 1 0 0 SCI_0 (TXI_0)
1 1 0 1 SCI_0 (RXI_0)
1 1 1 0 SCI_1 (TXI_1)
1 1 1 1 SCI_1 (RXI_1)
7
DL
0
R/W DREQ Level and DREQ Edge Select
6
DS
0
R/W Specify the detecting method of the DREQ pin input and
the detecting level.
If the transfer request source is specified as an on-chip
peripheral module or if an auto-request is specified, these
bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Rev. 4.00 Dec. 15, 2009 Page 391 of 1558
REJ09B0181-0400