SH7080_09 Datasheet, PDF (689/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input
capture transfer for channel 5.
Figures 11.126 and 11.127 show the timing in this case.
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 11.126 Contention between TGR Read and Input Capture (Channels 0 to 4)
TGR read cycle
T1 T2
MPφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
M
Figure 11.127 Contention between TGR Read and Input Capture (Channel 5)
Rev. 4.00 Dec. 15, 2009 Page 629 of 1558
REJ09B0181-0400