SH7080_09 Datasheet, PDF (778/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 14 Watchdog Timer (WDT)
Initial
Bit
Bit Name Value R/W Description
5
RSTS
0
R/W Reset Select
Selects the type of reset when the WTCNT overflows in
watchdog timer mode. In interval timer mode, this setting
is ignored.
0: Power-on reset
1: Manual reset
4
WOVF 0
R/W Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval timer
mode. This bit is not set in watchdog timer mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
2 to 0 CKS[2:0] 000
R/W Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is shown
inside the parenthesis in the table is the value when the
peripheral clock (Pφ) is 40 MHz.
000: Pφ (6.4 μs)
001: Pφ /4 (25.6 μs)
010: Pφ /16 (102.4 μs)
011: Pφ /32 (204.8 μs)
100: Pφ /64 (409.6 μs)
101: Pφ /256 (1.64 ms)
110: Pφ /1024 (6.55 ms)
111: Pφ /4096 (26.21 ms)
Note:
If bits CKS2 to CKS0 are modified when the WDT
is operating, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not operating.
Rev. 4.00 Dec. 15, 2009 Page 718 of 1558
REJ09B0181-0400