SH7080_09 Datasheet, PDF (195/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
For the mask ROM version, only the L-bus instruction-fetch address break (2 channels) is
available.
7.1 Features
The UBC has the following features:
1. The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break setting: channel A and then channel B match with break conditions,
but not in the same bus cycle).
⎯ Address
Comparison bits are maskable in 1-bit units.
One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be
selected.
⎯ Data
32-bit maskable.
One of the two data buses (L-bus data (LDB) and I-bus data (IDB)) can be selected.
⎯ Bus cycle
Instruction fetch or data access
⎯ Read/write
⎯ Operand size
Byte, word, and longword
2. A user-designed user-break interrupt exception processing routine can be run.
3. In an instruction fetch cycle, it can be selected that a user break is set before or after an
instruction is executed.
4. Maximum repeat times for the break condition (only for channel B): 2¹² – 1 times.
5. Four pairs of branch source/destination buffers (eight pairs for F-ZTAT version supporting full
functions of E10A).
Rev. 4.00 Dec. 15, 2009 Page 135 of 1558
REJ09B0181-0400