SH7080_09 Datasheet, PDF (1304/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
(3.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU)
This parameter indicates the return value of the program processing result.
Bit: 31
-
Initial value: -
R/W: R/W
30
-
-
R/W
29
-
-
R/W
28
-
-
R/W
27
-
-
R/W
26
-
-
R/W
25
-
-
R/W
24
-
-
R/W
23
-
-
R/W
22
-
-
R/W
21
-
-
R/W
20
-
-
R/W
19
-
-
R/W
18
-
-
R/W
17
-
-
R/W
16
-
-
R/W
Bit: 15
-
Initial value: -
R/W: R/W
14
-
-
R/W
13
-
-
R/W
12
-
-
R/W
11
-
-
R/W
10
-
-
R/W
9
-
-
R/W
8
-
-
R/W
7
-
-
R/W
6
MD
-
R/W
5
EE
-
R/W
4
FK
-
R/W
3
-
-
R/W
2
WD
-
R/W
1
WA
-
R/W
0
SF
-
R/W
Bit
Bit Name
31 to 7 ⎯
Initial
Value
R/W
Undefined R/W
6
MD
Undefined R/W
Description
Unused
Return 0.
Programming Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 23.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: FWE = 0 or FLER = 1, and programming cannot be
performed
Rev. 4.00 Dec. 15, 2009 Page 1244 of 1558
REJ09B0181-0400