SH7080_09 Datasheet, PDF (139/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Bit
8 to 6
5 to 3
2 to 0
Initial
Bit Name Value
PFC[2:0] 011
MIFC[2:0] 011
MPFC[2:0] 011
R/W Description
R/W Peripheral Clock (Pφ) Frequency Division Ratio
Specify the division ratio of the peripheral clock (Pφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/8
Other than above: Setting prohibited
R/W MTU2S Clock (MIφ) Frequency Division Ratio
Specify the division ratio of the MTU2S clock (MIφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/8
Other than above: Setting prohibited
R/W MTU2 Clock (MPφ) Frequency Division Ratio
Specify the division ratio of the MTU2 clock (MPφ)
frequency with respect to the output frequency of PLL
circuit. If a prohibited value is specified, subsequent
operation is not guaranteed.
000: ×1
001: ×1/2
010: ×1/3
011: ×1/4
100: ×1/8
Other than above: Setting prohibited
Rev. 4.00 Dec. 15, 2009 Page 79 of 1558
REJ09B0181-0400