SH7080_09 Datasheet, PDF (255/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.5.2 Transfer Information Writeback Skip Function
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer
information will not be written back. Table 8.5 shows the transfer information writeback skip
condition and writeback skipped registers. Note that the CRA and CRB are always written back.
The writeback of the MRA and MRB are always skipped.
Table 8.5 Transfer Information Writeback Skip Condition and Writeback Skipped
Registers
SM1
0
0
1
1
DM1
0
1
0
1
SAR
Skipped
Skipped
Written back
Written back
DAR
Skipped
Written back
Skipped
Written back
8.5.3 Normal Transfer Mode
In normal transfer mode, data are transferred in one byte, one word, or one longword units in
response to a single activation request. From 1 to 65,536 transfers can be specified. The transfer
source and destination addresses can be specified as incremented, decremented, or fixed. When the
specified number of transfers ends, an interrupt can be requested to the CPU.
Table 8.6 lists the register function in normal transfer mode. Figure 8.6 shows the memory map in
normal transfer mode.
Table 8.6 Register Function in Normal Transfer Mode
Register
Function
SAR
Source address
DAR
Destination address
CRA
Transfer count A
CRB
Transfer count B
Note: * Transfer information writeback is skipped.
Written Back Value
Incremented/decremented/fixed*
Incremented/decremented/fixed*
CRA − 1
Not updated
Rev. 4.00 Dec. 15, 2009 Page 195 of 1558
REJ09B0181-0400