SH7080_09 Datasheet, PDF (29/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Figures
Seion 1 Overview
Figure 1.1 Block Diagram ............................................................................................................ 7
Figure 1.2 Pin Assignments of SH7083 (TQFP1414-100) ........................................................... 8
Figure 1.3 Pin Assignments of SH7084........................................................................................ 9
Figure 1.4 Pin Assignments of SH7085...................................................................................... 10
Figure 1.5 Pin Assignments of SH7086...................................................................................... 11
Figure 1.6 Pin Assignments of SH7083 (P-LFBGA-112) .......................................................... 12
Section 2 CPU
Figure 2.1 CPU Internal Register Configuration ........................................................................ 24
Figure 2.2 Register Data Format ................................................................................................ 28
Figure 2.3 Memory Data Format ................................................................................................ 28
Figure 2.4 Transitions between Processing States...................................................................... 52
Section 3 MCU Operating Modes
Figure 3.1 Address Map for Each Operating Mode in SH7083
(256-Kbyte Flash Memory Version) ......................................................................... 58
Figure 3.2 Address Map for Each Operating Mode in SH7083
(512-Kbyte Flash Memory Version) ......................................................................... 59
Figure 3.3 Address Map for Each Operating Mode in SH7084
(256-Kbyte Flash Memory Version) ......................................................................... 60
Figure 3.4 Address Map for Each Operating Mode in SH7084
(512-Kbyte Flash Memory Version) ......................................................................... 61
Figure 3.5 Address Map for Each Operating Mode in SH7085
(256-Kbyte Flash Memory Version) ......................................................................... 62
Figure 3.6 Address Map for Each Operating Mode in SH7085
(512-Kbyte Flash Memory Version) ......................................................................... 63
Figure 3.7 Address Map for Each Operating Mode in SH7086.................................................. 64
Figure 3.8 Reset Input Timing when Changing Operating Mode............................................... 65
Section 4 Clock Pulse Generator (CPG)
Figure 4.1 Block Diagram of Clock Pulse Generator ................................................................. 68
Figure 4.2 Connection of Crystal Resonator (Example)............................................................. 82
Figure 4.3 Crystal Resonator Equivalent Circuit........................................................................ 82
Figure 4.4 Example of External Clock Connection .................................................................... 83
Figure 4.5 Cautions for Oscillator Circuit Board Design ........................................................... 85
Figure 4.6 Recommended External Circuitry around PLL ......................................................... 86
Rev. 4.00 Dec. 15, 2009 Page xxvii of lviii
REJ09B0181-0400