SH7080_09 Datasheet, PDF (213/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
10
PCBA
0
R/W PC Break Select A
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
execution
1: PC break of channel A is set after instruction
execution
9, 8
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7
DBEA
0
R/W Data Break Enable A
Selects whether or not the data bus condition is
included in the break condition of channel A.
0: No data bus condition is included in the condition of
channel A
1: The data bus condition is included in the condition of
channel A
6
PCBB
0
R/W PC Break Select B
Selects the break timing of the instruction fetch cycle
for channel B as before or after instruction execution.
0: PC break of channel B is set before instruction
execution
1: PC break of channel B is set after instruction
execution
5
DBEB
0
R/W Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
channel B
1: The data bus condition is included in the condition of
channel B
4
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 153 of 1558
REJ09B0181-0400