SH7080_09 Datasheet, PDF (111/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles T Bit
STS MACH,Rn
MACH → Rn
0000nnnn00001010 1
⎯
STS MACL,Rn
MACL → Rn
0000nnnn00011010 1
⎯
STS PR,Rn
PR → Rn
0000nnnn00101010 1
⎯
STS.L MACH,@–Rn
Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 1
⎯
STS.L MACL,@–Rn
Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 1
⎯
STS.L PR,@–Rn
Rn–4 → Rn, PR → (Rn) 0100nnnn00100010 1
⎯
TRAPA #imm
PC/SR → Stack area,
11000011iiiiiiii 8
⎯
(imm × 4 + VBR) → PC
Note: * Number of execution cycles until this LSI enters sleep mode.
About the number of execution cycles:
The table lists the minimum number of execution cycles. In practice, the number of
execution cycles will be increased depending on the conditions such as:
• When there is a conflict between instruction fetch and data access
• When the destination register of a load instruction (memory → register) is also used
by the instruction immediately after the load instruction.
Rev. 4.00 Dec. 15, 2009 Page 51 of 1558
REJ09B0181-0400