SH7080_09 Datasheet, PDF (241/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2.8 DTC Control Register (DTCCR)
DTCCR specifies transfer information read skip.
Bit: 7
6
5
4
3
2
1
0
-
-
-
RRS RCHNE -
-
ERR
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R
R R/(W)*
Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Initial
Bit
Bit Name Value R/W Description
7 to 5 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
RRS
0
R/W DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer information
read. A DTC vector number is always compared with the
vector number for the previous activation. If the vector
numbers match and this bit is set to 1, the DTC data
transfer is started without reading a vector address and
transfer information. If the previous DTC activation is a
chain transfer, the vector address read and transfer
information read are always performed.
However, when the DTPR bit in the bus function
extending register (BSCEHR) is set to 1, transfer
information read skip is not performed regardless of the
setting of this bit.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
numbers match.
3
RCHNE 0
R/W Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer counter
(CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the chain
transfer is enabled when CRAH is written to CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
Rev. 4.00 Dec. 15, 2009 Page 181 of 1558
REJ09B0181-0400