SH7080_09 Datasheet, PDF (959/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.6 Usage Notes
17.6.1 Module Standby Mode Setting
The SSU operation can be disabled or enabled using the standby control register. The initial
setting is for SSU operation to be halted. Access to registers is enabled by clearing module
standby mode. For details, refer to section 26, Power-Down Modes.
17.6.2 Access to SSTDR and SSRDR Registers
Do not access SSTDR and SSRDR registers not validated by the setting of the DATS bits of the
SSCRL register. If accessed, transmission or reception thereafter may not be performed normally.
17.6.3 Continuous Transmission/Reception in SSU Slave Mode
During continuous transmission/reception in SSU slave mode, negate the SCS pin (high level) for
every frame. If the SCS pin is kept asserted (low level) for more than one frame, transmission or
reception cannot be performed correctly.
17.6.4 Note for Reception Operations in SSU Slave Mode
In continuous reception when slave reception in SSU mode has been selected, read the SS receive-
data register (SSRDR) before each next round of reception starts (i.e. before an externally
connected master device starts a next round of transmission).
If the next round of reception starts after the SS status register receive-data full (RDRF) bit has
been set to 1 but before the SSRDR has been read, and the SSRDR is read before the reception of
one frame is complete, the conflict/incomplete error bit in SSSR will be set to 1 on completion of
reception.
Furthermore, when the next round of reception starts after the receive-data full (RDRF) bit has
been set to 1 and before the SSRDR has been read, and the SSRDR has not been read by the end
of the reception of the frame, the CE and overflow-error (ORER) bits will not have been set, but
the received data will be discarded.
Further note that this point for caution does not apply to simultaneous transmission and reception
in SSU slave mode or to clock-synchronous mode.
Rev. 4.00 Dec. 15, 2009 Page 899 of 1558
REJ09B0181-0400