SH7080_09 Datasheet, PDF (966/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Bit
6
5
4
3 to 0
Bit Name
RCVD
Initial
Value
0
MST
0
TRS
0
CKS[3:0] 0000
R/W Description
R/W Reception Disable
When TRS = 0, this bit enables or disables continuous
reception without reading of ICDRR. In master receive
mode, when ICDRR cannot be read before the rising
edge of the 8th clock of SCL, set RCVD to 1 so that
data is received in byte units.
0: Enables continuous reception
1: Disables continuous reception
R/W Master/Slave Select
R/W Transmit/Receive Select
In master mode with the I²C bus format, when
arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode.
Modification of the TRS bit should be made between
transfer frames.
When seven bits after the start condition is issued in
slave receive mode match the slave address set to
SAR and the 8th bit is set to 1, TRS is automatically
set to 1. If an overrun error occurs in master receive
mode with the clock synchronous serial format, MST is
cleared and the mode changes to slave receive mode.
Operating modes are described below according to
MST and TRS combination. When clock synchronous
serial format is selected and MST = 1, clock is output.
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
R/W Transfer Clock Select 3 to 0
These bits should be set according to the necessary
transfer rate (table 18.3) in master mode. In slave
mode, these bits should be used to specify the data
setup time in transmission mode. The setup time is set
to 10 tpcyc when CKS3 = 0 or 20 tpcyc when CKS3 =
1 (tpcyc is one Pφ cycle).
Rev. 4.00 Dec. 15, 2009 Page 906 of 1558
REJ09B0181-0400