SH7080_09 Datasheet, PDF (1318/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
(2) Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 23.11.
Start programming
procedure program
Select on-chip program
to be downloaded and
set download destination
by FTDAR
(2.1)
Set FKEY to H'A5
After clearing VBR,
set SCO to 1 and
execute download
(2.2)
(2.3)
Clear FKEY to 0
(2.4)
DPFR=0?
Yes
(2.5)
No
Download error processing
Set the FPEFEQ and
FUBRA parameters
(2.6)
Initialization
JSR FTDAR setting+32 (2.7)
FPFR=0?
Yes
1
(2.8)
No
Initialization error processing
1
Set FKEY to H'5A
(2.9)
Set parameter to R4 and
R5 (FMPAR and FMPDR)
(2.10)
Programming
JSR FTDAR setting+16
(2.11)
FPFR=0?
(2.12)
No
Yes
Clear FKEY and
programming
error processing
No
Required data
programming is
(2.13)
completed?
Yes
Clear FKEY to 0
(2.14)
End programming
procedure program
Figure 23.11 Programming Procedure
The details of the programming procedure are described below. The procedure program must
be executed in an area other than the flash memory to be programmed. Especially the part
where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM.
Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock
(Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value.
The area that can be executed in the steps of the user procedure program (on-chip RAM, user
MAT, and external space) is shown in section 23.9.2, Areas for Storage of the Procedural
Program and Data for Programming.
Rev. 4.00 Dec. 15, 2009 Page 1258 of 1558
REJ09B0181-0400