SH7080_09 Datasheet, PDF (952/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.4.7 Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1) Initial Settings in Clock Synchronous Communication Mode
Figure 17.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note:
Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1] Set PFC for external pins to be used
(SSCK, SSI, SSO, and SCS)
[2]
Specify MSS in SSCRH
[3]
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
[4]
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
[1] Make appropriate settings in the PFC for the external
pins to be used.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[5] Specify timing of TEND bit setting, SCS pin assertion, and data
output on the SSO pin.
[6] Enables/disables interrupt requests to the CPU.
[5]
Specify bits TENDSTS, SCSATS,
and SSODTS in SSCR2
[6]
Specify bits TE, RE, TEIE, TIE, RIE,
and CEIE in SSER simultaneously
End
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode
Rev. 4.00 Dec. 15, 2009 Page 892 of 1558
REJ09B0181-0400