SH7080_09 Datasheet, PDF (987/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Slave receive mode
SCL
(Master output)
SDA
(Master output)
SCL
(Slave output)
SDA
(Slave output)
TDRE
TEND
Slave transmit mode
9
1
2
3
4
5
6
7
8
9
1
A
A
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7
TRS
ICDRT
Data 1
Data 2 Data 3
ICDRS
Data 1
Data 2
ICDRR
User
processing ^{[2] Write data to ICDRT (data 1)}
[2] Write data to ICDRT (data 2)
[2] Write data to ICDRT (data 3)
Figure 18.9 Slave Transmit Mode Operation Timing (1)
Rev. 4.00 Dec. 15, 2009 Page 927 of 1558
REJ09B0181-0400