SH7080_09 Datasheet, PDF (431/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
• When activation request is generated in the order of DMAC and DTC during external space access from CPU
Transfer is started for the request that is generated first
Internal bus
External space access from CPU
DMAC
DTC
DTC activation request
DMAC activation request
• When activation request is generated in the order of DTC and DMAC during external space access from CPU
Transfer is started for the request that is generated first
Internal bus
External space access from CPU
DTC
DMAC
DTC activation request
DMAC activation request
• When activation request is generated for DTC and DMAC at the same time during external space access from CPU
Transfer is started in accordance with the bus priority (DTC>DMAC)
Internal bus
External space access from CPU
DTC
DMAC
DTC activation request
Priority determination
DMAC activation request
[Reference] When activation request is generated in the order of DMAC and DTC during access to an on-chip peripheral module by CPU
Transfer is started in accordance with the bus priority (DTC>DMAC)
Internal bus
Access to on-chip peripheral module from CPU
DTC
DMAC
DTC activation request
DMAC activation request
Priority determination
Figure 9.49 Bus Arbitration when DTC and DMAC Compete during External Space Access
from CPU
Rev. 4.00 Dec. 15, 2009 Page 371 of 1558
REJ09B0181-0400