SH7080_09 Datasheet, PDF (904/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Figure 16.12 shows a sample flowchart for initializing the SCIF.
Start of initialization
Clear TE and RE bits
in SCSCR to 0
[1]
Set TFRST and RFRST bits
in SCFCR to 1 to clear
the FIFO buffer
After reading BRK, DR,
and ER flags in SCFSR
and a flag in SCLSR,
write 0 to clear them
Set data transfer format
[2]
in SCSMR
Set CKE1 and CKE0 bits
in SCSCR (leaving TE, RE, TIE, [3]
and RIE bits cleared to 0)
Set value in SCBRR
[4]
Wait
No
1-bit interval elapsed?
Yes
Set RTRG1-0 and TTRG1-0 bits
in SCFCR, and clear TFRST
and RFRST bits to 0
[1] Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
[2] Set the data transfer format in
SCSMR.
[3] Set the CKE1 and CKE0 bits.
[4] Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used. Wait at least one
bit interval after this write before
moving to the next step.
[5] Make appropriate settings in the
PFC for the external pins to be used.
[6] Set the TE or RE bit in SCSCR
to 1. Also set the TEI, RIE, and
REIE bits to enable the TXD,
RXD, and SCK pins to be used.
When transmitting, the TXD pin
will go to the mark state.
When receiving in clock synchronous
mode with the synchronization clock
output (clock master) selected, a
clock starts to be output from the
SCK pin at this point.
Set PFC for external pins
to be used
[5]
(SCK, TXD, RXD, CTS, and RTS)
Set TE and RE bits in SCSCR
to 1, and set TIE, RIE,
[6]
and REIE bits
End of initialization
Figure 16.12 Sample Flowchart for SCIF Initialization
Rev. 4.00 Dec. 15, 2009 Page 844 of 1558
REJ09B0181-0400