SH7080_09 Datasheet, PDF (960/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
17.6.5 Note on Master Transmission and Master Reception Operations in SSU Mode
To perform master transmission or reception in SSU mode, perform one of the following
operations:
• After the TDRE flag in the SSSR register is set to 1, store the next byte of transmit data in
SSTDR before transmission of the second to last bit starts.
• Store the next byte of transmit data in SSTDR after confirming that the TEND flag in the
SSSR register has been set to 1.
• Use the SSU with TENDSTS in the SSCR2 register cleared to 0, or with both TENDSTS and
SCSATS in the SSCR2 register set to 1.
17.6.6 Note on DTC Transfers
When a DTC transfer occurs with SSTXI as the activation source, TDRE is not cleared when the
transfer counter reaches H'0000 but communication operation starts anyway.
When using the SSTXI interrupt to clear the flag, perform interrupt handling first.
However, do not clear the flag within the SSTXI interrupt handler when the initial value of the
DTC’s transfer counter is set to H'0001 and DISEL is set to 1. In this case, clearing the flag by the
interrupt handler may cause the SSU to start communication operation a second time.
Rev. 4.00 Dec. 15, 2009 Page 900 of 1558
REJ09B0181-0400