SH7080_09 Datasheet, PDF (1617/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

SCSPTR and SCI pins ............................ 782
SCSPTR and SCIF pins .......................... 851
Self-refreshing ........................................ 332
Sending a break signal ............................ 785
Sequential break ..................................... 161
Serial communication interface
(SCI) ....................................................... 723
Serial communication interface
with FIFO (SCIF) ................................... 789
Shift instructions....................................... 48
Single address mode ............................... 409
Single chip mode ...................................... 57
Single mode ............................................ 962
Single read .............................................. 320
Single write............................................. 323
Single-cycle scan mode .......................... 963
Sleep mode ........................................... 1338
Software protection............................... 1272
Software standby mode......................... 1339
SRAM interface with byte selection ....... 339
SSU Interrupt sources ............................. 898
SSU mode ............................................... 881
Stack after interrupt exception
handling .................................................. 130
Stack states after exception
handling ends.......................................... 100
Status register (SR) ................................... 25
Synchronous serial communication
unit (SSU) ............................................... 859
System control instructions....................... 50
T
Target pins and conditions for high-
impedance control................................... 705
The address map for the operating
modes ........................................................ 58
Transfer clock ......................................... 876
Transfer information read skip
function ................................................... 194
Transfer information writeback skip
function ................................................... 195
Trap instructions ....................................... 97
U
User boot mode ..................................... 1266
User break controller (UBC)................... 135
User break interrupt ................................ 122
User MAT ............................................. 1222
User program mode............................... 1256
Using interval timer mode....................... 721
Using watchdog timer mode ................... 720
V
Vector numbers and vector table address
offsets........................................................ 89
Vector-base register (VBR) ...................... 26
W
Wait between access cycles .................... 357
Watchdog timer (WDT) .......................... 713
Rev. 4.00 Dec. 15, 2009 Page 1557 of 1558
REJ09B0181-0400